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          FSMC扩展外部SRAM
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        <p>​        原文地址：<a target="_blank" rel="noopener" href="https://doc.embedfire.com/mcu/stm32/f4/hal_general/zh/latest/doc/chapter26_0/chapter26_0.html">https://doc.embedfire.com/mcu/stm32/f4/hal_general/zh/latest/doc/chapter26_0/chapter26_0.html</a></p>
<h3 id="SRAM信号线"><a href="#SRAM信号线" class="headerlink" title="SRAM信号线"></a>SRAM信号线</h3><table>
<thead>
<tr>
<th>信号线</th>
<th>类型</th>
<th>说明</th>
</tr>
</thead>
<tbody><tr>
<td>A0-A18</td>
<td>I</td>
<td>地址输入</td>
</tr>
<tr>
<td>I/O0-I/O7</td>
<td>I/O</td>
<td>数据输入输出信号，低字节</td>
</tr>
<tr>
<td>I/O8-I/O15</td>
<td>I/O</td>
<td>数据输入输出信号，高字节</td>
</tr>
<tr>
<td>CS和CS1#</td>
<td>I</td>
<td>片选信号，CS2高电平有效，CS1#低电平有效，部分芯片只有其中一个引脚</td>
</tr>
<tr>
<td>OE#</td>
<td>I</td>
<td>输出使能信号，低电平有效</td>
</tr>
<tr>
<td>WE#</td>
<td>I</td>
<td>写入使能，低电平有效</td>
</tr>
<tr>
<td>UB#</td>
<td>I</td>
<td>数据掩码信号Upper Byte，高位字节允许访问，低电平有效</td>
</tr>
<tr>
<td>LB#</td>
<td>I</td>
<td>数据掩码信号Lower Byte，低位字节允许访问，低电平有效</td>
</tr>
</tbody></table>
<p>​        SRAM的控制比较简单，只要控制信号线使能了访问，从地址线输入要访问的地址，即可从I/O数据线写入或读出数据。</p>
<h3 id="控制电路"><a href="#控制电路" class="headerlink" title="控制电路"></a>控制电路</h3><p>​        控制电路主要包含了片选、读写使能以及上面提到的宽度控制信号UB#和LB#。利用CS2或CS1#片选信号，可以把多个SRAM芯片组成一个大容量的内存条。OE#和WE#可以控制读写使能，防止误操作。</p>
<h3 id="SRAM的读写流程"><a href="#SRAM的读写流程" class="headerlink" title="SRAM的读写流程"></a>SRAM的读写流程</h3><p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_20221023213318.png"></p>
<p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/%E5%BE%AE%E4%BF%A1%E6%88%AA%E5%9B%BE_20221023213345.png"></p>
<p>读写时序的流程很类似，下面我们统一解说：</p>
<ol>
<li><p>主机使用地址信号线发出要访问的存储器目标地址；</p>
</li>
<li><p>控制片选信号CS1#及CS2#使能存储器芯片；</p>
</li>
<li><p>若是要进行读操作，则控制读使能信号OE#表示要读数据，若进行写操作则控制写使能信号WE#表示要写数据；</p>
</li>
<li><p>使用掩码信号LB#与UB#指示要访问目标地址的高、低字节部分；</p>
</li>
<li><p>若是读取过程，存储器会通过数据线向主机输出目标数据，若是写入过程，主要使用数据线向存储器传输目标数据。</p>
</li>
</ol>
<p>​        在读写时序中，有几个比较重要的时间参数，在使用STM32 控制的时候需要参考，它们的介绍见表 26‑2。</p>
<table>
<thead>
<tr>
<th>时间参数</th>
<th>IS62WV51216BLL-55ns型号的时间要求</th>
<th>说明</th>
</tr>
</thead>
<tbody><tr>
<td>tRC</td>
<td>不小于55ns</td>
<td>读操作的总时间</td>
</tr>
<tr>
<td>tAA</td>
<td>最迟不大于55ns</td>
<td>从接收到地址信号到给出有效数据的时间</td>
</tr>
<tr>
<td>tDOE</td>
<td>最迟不大于25ns</td>
<td>从接收到读使能信号到给出有效数据的时间</td>
</tr>
<tr>
<td>tWC</td>
<td>不小于55ns</td>
<td>写操作的总时间</td>
</tr>
<tr>
<td>tSA</td>
<td>大于0ns</td>
<td>从发送地址信号到给出写有使能信号的时间</td>
</tr>
<tr>
<td>tPWE</td>
<td>不小于40ns</td>
<td>从接收到写使能信号到数据采样的时间</td>
</tr>
</tbody></table>
<h3 id="FSMC中的SRAM控制信号线"><a href="#FSMC中的SRAM控制信号线" class="headerlink" title="FSMC中的SRAM控制信号线"></a>FSMC中的SRAM控制信号线</h3><table>
<thead>
<tr>
<th>FSMC引脚名称</th>
<th>对应SRAM引脚名</th>
<th>说明</th>
</tr>
</thead>
<tbody><tr>
<td>FSMC_NBL[1:0]</td>
<td>LB#、UB#</td>
<td>数据掩码信号</td>
</tr>
<tr>
<td>FSMC_A[18:0]</td>
<td>A[18:0]</td>
<td>行地址线</td>
</tr>
<tr>
<td>FSMC_D[15:0]</td>
<td>I/O[15:0]</td>
<td>数据线</td>
</tr>
<tr>
<td>FSMC_NWE</td>
<td>WE#</td>
<td>写入使能</td>
</tr>
<tr>
<td>FSMC_NOE</td>
<td>OE#</td>
<td>输出使能(读使能)</td>
</tr>
<tr>
<td>FSMC_NE[1:4]</td>
<td>CE#</td>
<td>片选信号</td>
</tr>
</tbody></table>
<p>​        其中比较特殊的FSMC_NE是用于控制SRAM芯片的片选控制信号线，STM32具有FSMC_NE1/2/3/4号引脚，不同的引脚对应STM32内部不同的地址区域。例如，当STM32访问0x6C000000-0x6FFFFFFF地址空间时，FSMC_NE3引脚会自动设置为低电平，由于它连接到SRAM的CE#引脚，所以SRAM的片选被使能，而访问0x60000000-0x63FFFFFF地址时，FSMC_NE1会输出低电平。当使用不同的FSMC_NE引脚连接外部存储器时，STM32访问SRAM的地址不一样，从而达到控制多块SRAM芯片的目的。</p>
<h3 id="FSMC控制SRAM的时序"><a href="#FSMC控制SRAM的时序" class="headerlink" title="FSMC控制SRAM的时序"></a>FSMC控制SRAM的时序</h3><p>​        FSMC外设支持输出多种不同的时序以便于控制不同的存储器，它具有ABCD四种模式，下面我们仅针对控制SRAM使用的模式A进行讲解</p>
<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20221023213842.png" style="zoom:70%;">

<img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/微信截图_20221023213921.png" style="zoom:70%;">

<p>​        当内核发出访问某个指向外部存储器地址时，FSMC外设会根据配置控制信号线产生时序访问存储器，上图中的是访问外部SRAM时FSMC外设的读写时序。</p>
<p>​        以读时序为例，该图表示一个存储器操作周期由地址建立周期(ADDSET)、数据建立周期(DATAST)以及2个HCLK周期组成。在地址建立周期中，地址线发出要访问的地址，数据掩码信号线指示出要读取地址的高、低字节部分，片选信号使能存储器芯片；地址建立周期结束后读使能信号线发出读使能信号，接着存储器通过数据信号线把目标数据传输给FSMC，FSMC把它交给内核。</p>
<p>​        写时序类似，区别是它的一个存储器操作周期仅由地址建立周期(ADDSET)和数据建立周期(DATAST)组成，且在数据建立周期期间写使能信号线发出写信号，接着FSMC把数据通过数据线传输到存储器中。</p>
<h3 id="SRAM时序结构体"><a href="#SRAM时序结构体" class="headerlink" title="SRAM时序结构体"></a>SRAM时序结构体</h3><figure class="highlight c"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br></pre></td><td class="code"><pre><span class="line"><span class="keyword">typedef</span> <span class="class"><span class="keyword">struct</span></span></span><br><span class="line"><span class="class">&#123;</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_AddressSetupTime;       <span class="comment">/*地址建立时间，0-0xF个HCLK周期*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_AddressHoldTime;        <span class="comment">/*地址保持时间，0-0xF个HCLK周期*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_DataSetupTime;           <span class="comment">/*地址建立时间，0-0xF个HCLK周期*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_BusTurnAroundDuration;<span class="comment">/*总线转换周期,0-0xF个HCLK周期，在NOR FLASH */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_CLKDivision;<span class="comment">/*时钟分频因子,1-0xF，若控制异步存储器，本参数无效 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_DataLatency;    <span class="comment">/*数据延迟时间，若控制异步存储器，本参数无效 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> FSMC_AccessMode;             <span class="comment">/*设置访问模式 */</span></span><br><span class="line">&#125;FSMC_NORSRAMTimingInitTypeDef;</span><br></pre></td></tr></table></figure>
<ol>
<li>FSMC_AddressSetupTime</li>
</ol>
<blockquote>
<p>本成员设置地址建立时间，即FSMC读写时序中的ADDSET值，它可以被设置为0-0xF个HCLK周期数，按STM32HAL库的默认配置，HCLK的时钟频率为168MHz，即一个HCLK周期为1/168微秒。</p>
</blockquote>
<ol>
<li>FSMC_AddressHoldTime</li>
</ol>
<blockquote>
<p>本成员设置地址保持时间，它可以被设置为0-0xF个HCLK周期数。</p>
</blockquote>
<ol>
<li>FSMC_DataSetupTime</li>
</ol>
<blockquote>
<p>本成员设置数据建立时间，即FSMC读写时序中的DATAST值，它可以被设置为0-0xF个HCLK周期数。</p>
</blockquote>
<ol>
<li>FSMC_BusTurnAroundDuration</li>
</ol>
<blockquote>
<p>本成员设置总线转换周期，在NOR FLASH存储器中，地址线与数据线可以分时复用，总线转换周期就是指总线在这两种状态间切换需要的延时， 防止冲突。控制其它存储器时这个参数无效，配置为0即可。</p>
</blockquote>
<ol>
<li>FSMC_CLKDivision</li>
</ol>
<blockquote>
<p>本成员用于设置时钟分频，它以HCLK时钟作为输入，经过FSMC_CLKDivision分频后输出到FSMC_CLK引脚作为通讯使用的同步时钟。控制其它异步通讯的存储器时这个参数无效，配置为0即可。</p>
</blockquote>
<ol>
<li>FSMC_DataLatency</li>
</ol>
<blockquote>
<p>本成员设置数据保持时间，它表示在读取第一个数据之前要等待的周期数，该周期指同步时钟的周期，本参数仅用于同步NOR FLASH类型的存储器，控制其它类型的存储器时，本参数无效。</p>
</blockquote>
<ol>
<li>FSMC_AccessMode</li>
</ol>
<blockquote>
<p>本成员设置存储器访问模式，不同的模式下FSMC访问存储器地址时引脚输出的时序不一样，可选FSMC_ACCESS_MODE_A/B/C/D模式。一般来说控制SRAM时使用A模式。</p>
</blockquote>
<h3 id="SRAM初始化结构体"><a href="#SRAM初始化结构体" class="headerlink" title="SRAM初始化结构体"></a>SRAM初始化结构体</h3><figure class="highlight c"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br><span class="line">25</span><br><span class="line">26</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">/**</span></span><br><span class="line"><span class="comment">* @brief  FSMC NOR/SRAM Init structure definition</span></span><br><span class="line"><span class="comment">*/</span></span><br><span class="line"><span class="keyword">typedef</span> <span class="class"><span class="keyword">struct</span></span></span><br><span class="line"><span class="class">&#123;</span></span><br><span class="line">   <span class="keyword">uint32_t</span> NSBank;                <span class="comment">/*设置要控制的Bank区域 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> DataAddressMux;        <span class="comment">/*设置地址总线与数据总线是否复用 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> MemoryType;          <span class="comment">/*设置存储器的类型 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> MemoryDataWidth;     <span class="comment">/*设置存储器的数据宽度*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> BurstAccessMode;        <span class="comment">/*设置是否支持突发访问模式，只支持同步类型的存储器 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WaitSignalPolarity;  <span class="comment">/*设置等待信号的极性*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WrapMode;            <span class="comment">/*设置是否支持对齐的突发模式 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WaitSignalActive;    <span class="comment">/*配置等待信号在等待前有效还是等待期间有效 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WriteOperation;      <span class="comment">/*设置是否写使能 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WaitSignal;          <span class="comment">/*设置是否使能等待状态插入 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> ExtendedMode;        <span class="comment">/*设置是否使能扩展模式 */</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WriteBurst;          <span class="comment">/*设置是否使能写突发操作*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> AsynchronousWait;    <span class="comment">/*设置是否使能等待信号*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> ContinuousClock;     <span class="comment">/*设置是否使能FMC时钟输出到外部存储设备*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> WriteFifo;           <span class="comment">/*设置是否使能FIFO*/</span></span><br><span class="line">   <span class="keyword">uint32_t</span> PageSize;            <span class="comment">/*指定页的大小*/</span></span><br><span class="line">   <span class="comment">/*当不使用扩展模式时，本参数用于配置读写时序，否则用于配置读时序*/</span></span><br><span class="line">   FSMC_NORSRAM_TimingTypeDef* FSMC_ReadWriteTimingStruct;</span><br><span class="line">   <span class="comment">/*当使用扩展模式时，本参数用于配置写时序*/</span></span><br><span class="line">   FSMC_NORSRAM_TimingTypeDef * FSMC_WriteTimingStruct;</span><br><span class="line">&#125; FSMC_NORSRAM_InitTypeDef;</span><br></pre></td></tr></table></figure>
<ol>
<li>NSBank</li>
</ol>
<blockquote>
<p>本成员用于选择FSMC映射的存储区域，它的可选参数以及相应的内核地址映射范围见表 26‑4。</p>
<p>表 26‑4 可以选择的存储器区域及区域对应的地址范围</p>
</blockquote>
<table>
<thead>
<tr>
<th>可以输入的宏</th>
<th>对应的地址区域</th>
</tr>
</thead>
<tbody><tr>
<td>FSMC_Bank1_NORSRAM1</td>
<td>0x60000000-0x63FFFFFF</td>
</tr>
<tr>
<td>FSMC_Bank1_NORSRAM2</td>
<td>0x64000000-0x67FFFFFF</td>
</tr>
<tr>
<td>FSMC_Bank1_NORSRAM3</td>
<td>0x68000000-0x6BFFFFFF</td>
</tr>
<tr>
<td>FSMC_Bank1_NORSRAM4</td>
<td>0x6C000000-0x6FFFFFFF</td>
</tr>
</tbody></table>
<ol>
<li>DataAddressMux</li>
</ol>
<blockquote>
<p>本成员用于设置地址总线与数据总线是否复用(FSMC_DATA_ADDRESS_MUX_DISABLE /DISABLE)，在控制NOR FLASH时，可以地址总线与数据总线可以分时复用，以减少使用STM32信号线的数量。</p>
</blockquote>
<ol>
<li>MemoryType</li>
</ol>
<blockquote>
<p>本成员用于设置要控制的存储器类型，它支持控制的存储器类型为SRAM、PSRAM以及NOR FLASH(FSMC_MEMORY_TYPE_SRAM/PSRAM/NOR)。</p>
</blockquote>
<ol>
<li>MemoryDataWidth</li>
</ol>
<blockquote>
<p>本成员用于设置要控制的存储器的数据宽度，可选择设置成8或16位(FSMC_NORSRAM_MEM_BUS_WIDTH_8/16/32)。</p>
</blockquote>
<ol>
<li>BurstAccessMode</li>
</ol>
<blockquote>
<p>本成员用于设置是否使用突发访问模式(FSMC_BURST_ACCESS_MODE_DISABLE /DISABLE)，突发访问模式是指发送一个地址后连续访问多个数据，非突发模式下每访问一个数据都需要输入一个地址，仅在控制同步类型的存储器时才能使用突发模式。</p>
</blockquote>
<ol>
<li>AsynchronousWait</li>
</ol>
<blockquote>
<p>本成员用于设置是否使能在同步传输时使用的等待信号(FSMC_ASYNCHRONOUS_WAIT_DISABLE /DISABLE)，在控制同步类型的NOR或PSRAM时，存储器可以使用FSMC_NWAIT引脚通知STM32需要等待。</p>
</blockquote>
<ol>
<li>WaitSignalPolarity</li>
</ol>
<blockquote>
<p>本成员用于设置等待信号的有效极性，即要求等待时，使用高电平还是低电平(FSMC_WAIT_SIGNAL_POLARITY_LOW /HIGH)。</p>
</blockquote>
<ol>
<li>FSMC_WrapMode</li>
</ol>
<blockquote>
<p>本成员用于设置是否支持把非对齐的AHB突发操作分割成2次线性操作(FSMC_WRAP_MODE_DISABLE /ENABLE)，该配置仅在突发模式下有效。</p>
</blockquote>
<ol>
<li>WaitSignalActive</li>
</ol>
<blockquote>
<p>本成员用于配置在突发传输模式时，决定存储器是在等待状态之前的一个数据周期有效还是在等待状态期间有效(FSMC_WAIT_TIMING_BEFORE_WS / FSMC_WAIT_TIMING_DURING_WS)。</p>
</blockquote>
<ol>
<li>WriteOperation</li>
</ol>
<blockquote>
<p>这个成员用于设置是否写使能(FSMC_WRITE_OPERATION_DISABLE /ENABLE)，禁止写使能的话FSMC只能从存储器中读取数据，不能写入。</p>
</blockquote>
<ol>
<li>WaitSignal</li>
</ol>
<blockquote>
<p>本成员用于设置当存储器处于突发传输模式时，是否允许通过NWAIT信号插入等待状态(FSMC_WAIT_SIGNAL_ENABLE /DISABLE)。</p>
</blockquote>
<ol>
<li>ExtendedMode</li>
</ol>
<blockquote>
<p>本成员用于设置是否使用扩展模式(FSMC_EXTENDED_MODE_ENABLE /DISABLE)，在非扩展模式下，对存储器读写的时序都只使用FSMC_BCR寄存器中的配置，即下面的FSMC_ReadWriteTimingStruct结构体成员；在扩展模式下，对存储器的读写时序可以分开配置，读时序使用FSMC_BCR寄存器，写时序使用FSMC_BWTR寄存器的配置，即下面的FSMC_WriteTimingStruct结构体。</p>
</blockquote>
<h3 id="读时序配置例子"><a href="#读时序配置例子" class="headerlink" title="读时序配置例子"></a>读时序配置例子</h3><p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/image121.jpeg"></p>
<blockquote>
<h3 id="表-SRAM的读操作参数-时间要求摘自《IS62WV51216》规格书"><a href="#表-SRAM的读操作参数-时间要求摘自《IS62WV51216》规格书" class="headerlink" title="表 SRAM的读操作参数(时间要求摘自《IS62WV51216》规格书)"></a>表 SRAM的读操作参数(时间要求摘自《IS62WV51216》规格书)</h3></blockquote>
<table>
<thead>
<tr>
<th>时间参数</th>
<th>SRAM要求</th>
<th>说明</th>
<th>FSMC配置要求表达式</th>
</tr>
</thead>
<tbody><tr>
<td>tRC</td>
<td>不小于55ns</td>
<td>读操作周期</td>
<td>ADDSET+1+DATAST+1+2 &gt; 55ns</td>
</tr>
<tr>
<td>小于tLZCE</td>
<td>SRAM无给出要求</td>
<td>从发出地址到给出读使能信号的时间</td>
<td>ADDSET+1 &gt; 0 ns</td>
</tr>
<tr>
<td>tDOE</td>
<td>最迟不大于25ns</td>
<td>从接收到读使能信号至给出有效数据的时间</td>
<td>DATAST+1 &gt; 25 ns</td>
</tr>
</tbody></table>
<p>​        根据FSMC配置表达式的配置要求把时间单位1/72微秒(即1000/72纳秒)代入，可求得ADDSET = 0，DATAST=1时即可符合要求。如：</p>
<p>​        tRC=ADDSET+1+DATAST+1+2 =( 0+1+8+1+2 )*1000/168 = 71.4 ns &gt; 55 ns</p>
<p>​        tDOE=DATAST+1 = (8+1)*1000/168 = 53.5 &gt; 25 ns</p>
<p>​        可看出本实验中的配置有充足的裕量，裕量较大，可确保访问正确，但会导致访问速度变慢，可根据实际需要进行测试调整，保证访问正确的前提下可提高访问速度。</p>
<h3 id="写时序配置例子"><a href="#写时序配置例子" class="headerlink" title="写时序配置例子"></a>写时序配置例子</h3><p><img src="https://xdl-blog-picture.oss-cn-shanghai.aliyuncs.com/img/image131.jpeg"></p>
<p>表 SRAM的写操作参数(时间要求摘自《IS62WV51216》规格书)</p>
<table>
<thead>
<tr>
<th>时间参数</th>
<th>SRAM要求</th>
<th>说明</th>
<th>FSMC配置要求表达式</th>
</tr>
</thead>
<tbody><tr>
<td>tWC</td>
<td>大于55ns</td>
<td>写操作周期</td>
<td>ADDSET+1+DATAST+1 &gt; 55ns</td>
</tr>
<tr>
<td>tSA</td>
<td>无要求</td>
<td>地址建立时间</td>
<td>ADDSET+1 &gt; 0 ns</td>
</tr>
<tr>
<td>tPWB</td>
<td>最早最不小于40ns</td>
<td>从接收到写使能信号到对数据采样的时间</td>
<td>DATAST+1 &gt; 40 ns</td>
</tr>
</tbody></table>
<p>​        根据FSMC配置表达式的配置要求把时间单位1/72微秒(即1000/72纳秒)代入，可求得ADDSET = 0，DATAST=2时即可符合要求。如：</p>
<p>​        tWC = ADDSET+1+DATAST+1 =( 0+1+8+1 )*1000/168 = 59.5 ns &gt; 55 ns</p>
<p>​        tPWB = DATAST+1 = (8+1) *1000 / 168 = 53.5 &gt; 40 ns</p>
<p>​        把计算得的参数赋值到时序结构体中的AddressSetupTime（即ADDSET的值）及DataSetupTime（即DATAST的值）中，然后再把时序结构体作为指针赋值到FSMC初始化结构体中，作为读写的时序参数，最后再调用FSMC_NORSRAMInit函数即可把参数写入到相应的寄存器中。</p>

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